NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 536

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

EHCI Controller Registers (D29:F7)
14.1.19
14.1.20
536
PWR_CNTL_STS—Power Management Control/Status
Register (USB EHCI—D29:F7)
Address Offset:
Default Value:
NOTE: Reset (bits 15, 8): suspend well, and not D3-to-D0 warm reset nor core well reset.
DEBUG_CAPID—Debug Port Capability ID Register
(USB EHCI—D29:F7)
Address Offset:
Default Value:
14:13
12:9
Bit
7:2
1:0
Bit
7:0
15
8
PME Status — R/WC.
0 = Writing a 1 to this bit will clear it and cause the internal PME to de-assert (if enabled).
1 = This bit is set when the ICH6 EHC would normally assert the PME# signal independent of the
NOTE: This bit must be explicitly cleared by the operating system each time the operating system
Data Scale — RO. Hardwired to 00b indicating it does not support the associated Data register.
Data Select — RO. Hardwired to 0000b indicating it does not support the associated Data register.
PME Enable — R/W.
0 = Disable.
1 = Enable. Enables Intel
NOTE: This bit must be explicitly cleared by the operating system each time it is initially loaded.
Reserved
Power State — R/W. This 2-bit field is used both to determine the current power state of EHC
function and to set a new power state. The definition of the field values are:
00 = D0 state
11 = D3
If software attempts to write a value of 10b or 01b in to this field, the write operation must complete
normally; however, the data is discarded and no state change occurs. When in the D3
ICH6 must not accept accesses to the EHC memory range; but the configuration space must still be
accessible. When not in the D0 state, the generation of the interrupt output is blocked. Specifically,
the PIRQH is not asserted by the ICH6 when not in the D0 state.
When software changes this value from the D3
reset is generated, and software must re-initialize the function.
Debug Port Capability ID — RO. Hardwired to 0Ah indicating that this is the start of a Debug Port
Capability structure.
state of the PME_En bit.
HOT
is loaded.
54
0000h
58h
0Ah
state
–
55h
®
ICH6 EHC to generate an internal PME signal when PME_Status is 1.
Intel
Description
Description
®
HOT
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
state to the D0 state, an internal warm (soft)
R/W, R/WC, RO
16 bits
RO
8 bits
HOT
state, the