NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 336

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

PCI-to-PCI Bridge Registers (D30:F0)
9.1.20
336
SPDH—Secondary PCI Device Hiding Register
(PCI-PCI—D30:F0)
Offset Address:
Default Value:
This register allows software to hide the PCI devices, either plugged into slots or on the
motherboard.
15:8
Bit
Bit
3
2
1
0
7
6
5
4
3
2
1
0
VGA Enable (VGAE) — R/W. When set to a 1, the ICH6 PCI bridge forwards the following
transactions to PCI regardless of the value of the I/O base and limit registers. The transactions are
qualified by CMD.MSE (D30:F0:04 bit 1) and CMD.IOSE (D30:F0:04 bit 0) being set.
The same holds true from secondary accesses to the primary interface in reverse. That is, when the
bit is 0, memory and I/O addresses on the secondary interface between the above ranges will be
claimed.
ISA Enable (IE) — R/W. This bit only applies to I/O addresses that are enabled by the I/O Base and
I/O Limit registers and are in the first 64 KB of PCI I/O space. If this bit is set, the ICH6 PCI bridge
will block any forwarding from primary to secondary of I/O transactions addressing the last 768 bytes
in each 1-KB block (offsets 100h to 3FFh).
SERR# Enable (SEE) — R/W. This bit controls the forwarding of secondary interface SERR#
assertions on the primary interface. When set, the PCI bridge will forward SERR# pin.
Parity Error Response Enable (PERE) — R/W.
0 = Disable
1 = The ICH6 PCI bridge is enabled for parity error reporting based on parity errors on the PCI bus.
Reserved
Hide Device 7 (HD7) — R/W, RO. Same as bit 0 of this register, except for device 7 (AD[23])
Hide Device 6 (HD6) — R/W, RO. Same as bit 0 of this register, except for device 6 (AD[22])
Hide Device 5 (HD5) — R/W, RO. Same as bit 0 of this register, except for device 5 (AD[21])
Hide Device 4 (HD4) — R/W, RO. Same as bit 0 of this register, except for device 4 (AD[20])
Hide Device 3 (HD3) — R/W, RO. Same as bit 0 of this register, except for device 3 (AD[19])
Hide Device 2 (HD2) — R/W, RO. Same as bit 0 of this register, except for device 2 (AD[18])
Hide Device 1 (HD1) — R/W, RO. Same as bit 0 of this register, except for device 1 (AD[17])
Hide Device 0 (HD0) — R/W, RO.
0 = The PCI configuration cycles for this slot are not affected.
1 = Intel
• Memory addresses: 000A0000h-000BFFFFh
• I/O addresses: 3B0h-3BBh and 3C0h-3DFh. For the I/O addresses, bits [63:16] of the address
• SERR# is asserted on the secondary interface.
• This bit is set.
• CMD.SEE (D30:F0:04 bit 8) is set.
must be 0, and bits [15:10] of the address are ignored (i.e., aliased).
for configuration cycles to that device. Since the device will not see its IDSEL go active, it will
not respond to PCI configuration cycles and the processor will think the device is not present.
AD[16] is used as IDSEL for device 0.
®
ICH6 hides device 0 on the PCI bus. This is done by masking the IDSEL (keeping it low)
40–41h
00h
Intel
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
R/W, RO
16 bits