NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 209

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

5.20.10.1
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
The Debug port facilitates operating system and device driver debug. It allows the software to
communicate with an external console using a USB 2.0 connection. Because the interface to this
link does not go through the normal USB 2.0 stack, it allows communication with the external
console during cases where the operating system is not loaded, the USB 2.0 software is broken, or
where the USB 2.0 software is being debugged. Specific features of this implementation of a debug
port are:
There are two operational modes for the USB debug port:
Behavioral Rules
Theory of Operation
1. Mode 1 is when the USB port is in a disabled state from the viewpoint of a standard host
2. Mode 2 is when the host controller is running (i.e., host controller’s Run/Stop# bit is 1). In
1. In both modes 1 and 2, the Debug Port controller must check for software requested debug
2. If the debug port is enabled by the debug driver, and the standard host controller driver resets
3. If the standard host controller driver suspends the USB port, then USB debug transactions are
4. The ENABLED_CNT bit in the debug register space is independent of the similar port control
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Only works with an external USB 2.0 debug device (console)
Implemented for a specific port on the host controller
Operational anytime the port is not suspended AND the host controller is in D0 power state.
Capability is interrupted when port is driving USB RESET
controller driver. In Mode 1, the Debug Port controller is required to generate a “keepalive”
packets less than 2 ms apart to keep the attached debug device from suspending. The keepalive
packet should be a standalone 32-bit SYNC field.
Mode 2, the normal transmission of SOF packets will keep the debug device from suspending.
transactions at least every 125 microseconds.
the USB port, USB debug transactions are held off for the duration of the reset and until after
the first SOF is sent.
held off for the duration of the suspend/resume sequence and until after the first SOF is sent.
bit in the associated Port Status and Control register.
Functional Description
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