NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 578

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

SMBus Controller Registers (D31:F3)
15.2.16
15.2.17
578
Note: This register is in the resume well and is reset by RSMRST#.
Note: This register is in the resume well and is reset by RSMRST#.
SLV_CMD—Slave Command Register (SMBus—D31:F3)
Register Offset:
Default Value:
NOTIFY_DADDR—Notify Device Address Register
(SMBus—D31:F3)
Register Offset:
Default Value:
Bit
7:2
Bit
7:1
2
1
0
0
Reserved
SMBALERT_DIS — R/W.
0 = Allows the generation of the interrupt or SMI#.
1 = Software sets this bit to block the generation of the interrupt or SMI# due to the SMBALERT#
HOST_NOTIFY_WKEN — R/W. Software sets this bit to 1 to enable the reception of a Host Notify
command as a wake event. When enabled this event is “OR”ed in with the other SMBus wake
events and is reflected in the SMB_WAK_STS bit of the General Purpose Event 0 Status register.
0 = Disable
1 = Enable
HOST_NOTIFY_INTREN — R/W. Software sets this bit to 1 to enable the generation of interrupt or
SMI# when HOST_NOTIFY_STS (offset SMBASE + 10h, bit 0) is 1. This enable does not affect the
setting of the HOST_NOTIFY_STS bit. When the interrupt is generated, either PIRQB# or SMI# is
generated, depending on the value of the SMB_SMI_EN bit (D31:F3:40h, bit 1). If the
HOST_NOTIFY_STS bit is set when this bit is written to a 1, then the interrupt (or SMI#) will be
generated. The interrupt (or SMI#) is logically generated by AND’ing the STS and INTREN bits.
0 = Disable
1 = Enable
DEVICE_ADDRESS — RO. This field contains the 7-bit device address received during the Host
Notify protocol of the SMBus 2.0 Specification. Software should only consider this field valid when
the HOST_NOTIFY_STS bit (D31:F3:SMBASE +10, bit 0) is set to 1.
Reserved
source. This bit is logically inverted and ANDed with the SMBALERT_STS bit (offset SMBASE
+ 00h, bit 5). The resulting signal is distributed to the SMI# and/or interrupt generation logic.
This bit does not effect the wake logic.
SMBASE + 11h
00h
SMBASE + 14h
00h
Intel
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
R/W
8 bits
RO
8 bits