NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 119

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

5.5.1.5
5.5.1.6
5.5.1.7
5.5.1.8
Intel
Table 5-8. SYNC Bit Definition
®
I/O Controller Hub 6 (ICH6) Family Datasheet
SYNC
Valid values for the SYNC field are shown in
NOTES:
SYNC Time-Out
There are several error cases that can occur on the LPC interface. The ICH6 responds as defined in
section 4.2.1.9 of the Low Pin Count Interface Specification, Revision 1.1 to the stimuli described
therein. There may be other peripheral failure conditions; however, these are not handled by the
ICH6.
SYNC Error Indication
The ICH6 responds as defined in section 4.2.1.10 of the Low Pin Count Interface Specification,
Revision 1.1.
Upon recognizing the SYNC field indicating an error, the ICH6 treats this as an SERR by reporting
this into the Device 31 Error Reporting Logic.
LFRAME# Usage
The ICH6 follows the usage of LFRAME# as defined in the Low Pin Count Interface Specification,
Revision 1.1.
The ICH6 performs an abort for the following cases (possible failure cases):
1. All other combinations are RESERVED.
2. If the LPC controller receives any SYNC returned from the device other than short (0101), long wait (0110), or
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•
•
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Bits[3:0]
ready (0000) when running a FWH cycle, indeterminate results may occur. A FWH device is not allowed to
assert an Error SYNC.
ICH6 starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC after four
consecutive clocks.
ICH6 starts a Memory, I/O, or DMA cycle, and the peripheral drives an invalid SYNC pattern.
A peripheral drives an illegal address when performing bus master cycles.
A peripheral drives an invalid value.
0000
0101
0110
1001
1010
1,2
Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA request
de-assertion and no more transfers desired for that channel.
Short Wait: Part indicating wait-states. For bus master cycles, the Intel
this encoding. Instead, the ICH6 uses the Long Wait encoding (see next encoding below).
Long Wait: Part indicating wait-states, and many wait-states will be added. This encoding
driven by the ICH6 for bus master cycles, rather than the Short Wait (0101).
Ready More (Used only by peripheral for DMA cycle): SYNC achieved with no error and
more DMA transfers desired to continue after this transfer. This value is valid only on DMA
transfers and is not allowed for any other type of cycle.
Error: Sync achieved with error. This is generally used to replace the SERR# or IOCHK#
signal on the PCI/ISA bus. It indicates that the data is to be transferred, but there is a serious
error in this transfer. For DMA transfers, this not only indicates an error, but also indicates
DMA request de-assertion and no more transfers desired for that channel.
Table
5-8.
Indication
Functional Description
®
ICH6 does not use
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