NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 451

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

11.1.26
11.1.27
11.2
Intel
Table 11-2. Bus Master IDE I/O Registers
®
I/O Controller Hub 6 (ICH6) Family Datasheet
ATC—APM Trapping Control Register (IDE—D31:F1)
Address Offset:
Default Value:
ATS—APM Trapping Status Register (IDE—D31:F1)
Address Offset:
Default Value:
Bus Master IDE I/O Registers (IDE—D31:F1)
The bus master IDE function uses 16 bytes of I/O space, allocated via the BMIBA register, located
in Device 31:Function 1 Configuration space, offset 20h. All bus master IDE I/O space registers
can be accessed as byte, word, or DWord quantities. Reading reserved bits returns an
indeterminate, inconsistent value, and writes to reserved bits have no affect (but should not be
attempted). The description of the I/O registers is shown in
BMIBASE
+ Offset
Bit
7:2
Bit
7:2
04–07
1
0
1
0
00
01
02
03
Reserved
Slave Trap (PST) — R/W. This bit enables trapping and SMI# assertion on legacy I/O accesses to
1F0h–1F7h and 3F6h. The active device must be the slave device for the trap and/or SMI# to occur.
Master Trap (PMT) — R/W. This bit enables trapping and SMI# assertion on legacy I/O accesses to
1F0h–1F7h and 3F6h. The active device must be master device for the trap and/or SMI# to occur.
Reserved
Slave Trap Status (PSTS) — R/WC. This bit indicates that a trap occurred to the slave device
Master Trap Status (PMTS) — R/WC. This bit indicates that a trap occurred to the master device
Mnemonic
BMICP
BMISP
BMIDP
—
—
C0h
00h
C4h
00h
Bus Master IDE Command Primary
Reserved
Bus Master IDE Status Primary
Reserved
Bus Master IDE Descriptor Table Pointer Primary
Register Name
Description
Description
Attribute:
Size:
Attribute:
Size:
IDE Controller Registers (D31:F1)
Table
11-2.
R/W
8 bits
R/WC
8 bits
xxxxxxxxh
Default
00h
00h
00h
00h
R/WC
Type
R/W
R/W
RO
RO
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