NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 330

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

PCI-to-PCI Bridge Registers (D30:F0)
9.1.7
9.1.8
9.1.9
330
PMLT—Primary Master Latency Timer Register
(PCI-PCI—D30:F0)
Offset Address:
Default Value:
HEADTYP—Header Type Register (PCI-PCI—D30:F0)
Offset Address:
Default Value:
BNUM—Bus Number Register (PCI-PCI—D30:F0)
Offset Address:
Default Value:
23:16
15:8
Bit
6:0
Bit
7:0
Bit
7:3
2:0
7
Multi-Function Device (MFD) — RO. The value reported here depends upon the state of the AC ‘97
function hide (FD) register (Chipset Configuration Registers:Offset 3418h), per the following table:
Header Type (HTYPE) — RO. This 7-bit field identifies the header layout of the configuration space,
which is a PCI-to-PCI bridge in this case.
Subordinate Bus Number (SBBN) — R/W. Indicates the highest PCI bus number below the bridge.
Secondary Bus Number (SCBN) — R/W. Indicates the bus number of PCI.
Primary Bus Number (PBN) — RO. Hardwired to 00h for legacy software compatibility.
Master Latency Timer Count (MLTC) — RO. Reserved per the PCI Express* Base Specification,
Revision 1.0a .
Reserved
FD.AAD
0
0
1
1
0Dh
00h
0Eh
81h
18-1Ah
000000h
FD.AMD
0
1
0
1
MFD
1
1
1
0
Intel
Description
Description
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
24 bits
RO
8 bits
RO
8 bits
R/W, RO