NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 434

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
10.10.6
434
GPI_INV—GPIO Signal Invert Register
Offset Address:
Default Value:
Lockable:
31:16
15:13
11:8
Bit
7:0
12
Reserved
GP_INV[n] — R/W. These bits are used to allow both active-low and active-high inputs to cause
SMI# or SCI. Note that in the S0 or S1 state, the input signal must be active for at least two PCI
clocks to ensure detection by the ICH6. In the S3, S4 or S5 states the input signal must be active for
at least 2 RTC clocks to ensure detection. The setting of these bits has no effect if the corresponding
GPIO is programmed as an output. These bits correspond to GPI that are in the resume well, and
will be reset to their default values by RSMRST# or by a write to the CF9h register.
0 = The corresponding GPI_STS bit is set when the ICH6 detects the state of the input pin to be
1 = The corresponding GPI_STS bit is set when the ICH6 detects the state of the input pin to be
GP_INV[n] — R/W. These bits are used to allow both active-low and active-high inputs to cause
SMI# or SCI. Note that in the S0 or S1 state, the input signal must be active for at least two PCI
clocks to ensure detection by the ICH6. These bits correspond to GPI that are in the core well, and
will be reset to their default values by PLTRST#.
0 = The corresponding GPI_STS bit is set when the ICH6 detects the state of the input pin to be
1 = The corresponding GPI_STS bit is set when the ICH6 detects the state of the input pin to be
GP_INV[n] — R/W. These bits are used to allow both active-low and active-high inputs to cause
SMI# or SCI. Note that in the S0 or S1 state, the input signal must be active for at least two PCI
clocks to ensure detection by the ICH6. In the S3, S4 or S5 states the input signal must be active for
at least 2 RTC clocks to ensure detection. The setting of these bits has no effect if the corresponding
GPIO is programmed as an output. These bits correspond to GPI that are in the resume well, and
will be reset to their default values by RSMRST# or by a write to the CF9h register.
0 = The corresponding GPI_STS bit is set when the ICH6 detects the state of the input pin to be
1 = The corresponding GPI_STS bit is set when the ICH6 detects the state of the input pin to be
GP_INV[n] — R/W. These bits are used to allow both active-low and active-high inputs to cause
SMI# or SCI. Note that in the S0 or S1 state, the input signal must be active for at least two PCI
clocks to ensure detection by the ICH6. The setting of these bits will have no effect if the
corresponding GPIO is programmed as an output. These bits correspond to GPI that are in the core
well, and will be reset to their default values by PLTRST#.
0 = The corresponding GPI_STS bit is set when the ICH6 detects the state of the input pin to be
1 = The corresponding GPI_STS bit is set when the ICH6 detects the state of the input pin to be
high.
low.
high.
low.
high.
low.
high.
low.
GPIOBASE +2Ch
00000000h
No
Intel
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Attribute:
Size:
Power Well:
32-bit
See bit description
R/W