NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 339

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

9.1.23
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
BPS—Bridge Proprietary Status Register
(PCI-PCI—D30:F0)
Offset Address:
Default Value:
31:17
15:7
Bit
6:4
3:2
1:0
16
Reserved
PERR# Assertion Detected (PAD) — R/WC. This bit is set by hardware whenever the PERR# pin
is asserted on the rising edge of PCI clock. This includes cases in which the chipset is the agent
driving PERR#. It remains asserted until cleared by software writing a 1 to this location. When
enabled by the PERR#-to-SERR# Enable bit (in the Bridge Policy Configuration register), a 1 in this
bit can generate an internal SERR# and be a source for the NMI logic.
This bit can be used by software to determine the source of a system problem.
Reserved
Number of Pending Transactions (NPT) — RO. This read-only indicator tells debug software how
many transactions are in the pending queue. Possible values are:
000 = No pending transaction
001 = 1 pending transaction
010 = 2 pending transactions
011 = 3 pending transactions
100 = 4 pending transactions
101 = 5 pending transactions
110 - 111 = Reserved
NOTE: This field is not valid if DTC.MDT (offset 44h:bits 7:6) is any value other than ‘00’.
Reserved
Number of Active Transactions (NAT) — RO. This read-only indicator tells debug software how
many transactions are in the active queue. Possible values are:
00 = No active transactions
01 = 1 active transaction
10 = 2 active transactions
11 = Reserved
48
00000000h
–
4Bh
Description
Attribute:
Size:
PCI-to-PCI Bridge Registers (D30:F0)
R/WC, RO
32 bits
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