NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 457

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

12.1.2
12.1.3
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
DID—Device Identification Register (SATA—D31:F2)
Offset Address:
Default Value:
Lockable:
PCICMD—PCI Command Register (SATA–D31:F2)
Address Offset:
Default Value:
15:11
15:0
Bit
10
Bit
9
8
7
6
5
4
3
2
1
0
Reserved
Interrupt Disable — R/W. This bit disables pin-based INTx# interrupts. This bit has no effect on MSI
operation.
0 = Internal INTx# messages are generated if there is an interrupt and MSI is not enabled.
1 = Internal INTx# messages will not be generated.
Fast Back to Back Enable (FBE) — RO. Reserved as 0.
SERR# Enable (SERR_EN) — RO. Reserved as 0.
Wait Cycle Control (WCC) — RO. Reserved as 0.
Parity Error Response (PER) — R/W.
0 = Disabled. SATA controller will not generate PERR# when a data parity error is detected.
1 = Enabled. SATA controller will generate PERR# when a data parity error is detected.
VGA Palette Snoop (VPS) — RO. Reserved as 0.
Postable Memory Write Enable (PMWE) — RO. Reserved as 0.
Special Cycle Enable (SCE) — RO. Reserved as 0.
Bus Master Enable (BME) — R/W. This bit controls the ICH6’s ability to act as a PCI master for IDE
Bus Master transfers. This bit does not impact the generation of completions for split transaction
commands.
Memory Space Enable (MSE) — R/W / RO. This bit controls access to the SATA controller’s target
memory space (for AHCI). (ICH6-M/ICH6R only)
NOTE: When MAP.MV (offset 90:bits 1:0) is not 00h, this register is Read Only (RO). Software is
For ICH6, this bit is RO ‘0’, unless the SCRAE bit (offset 94h:bit 9) is set.
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as well as the
1 = Enable. Note that the Base Address register for the Bus Master registers should be
Device ID — RO. This is a 16-bit value assigned to the ICH6 SATA controller.
Bus Master I/O registers.
programmed before this bit is set.
responsible for clearing this bit before entering combined mode.
02
ICH6: 2651h
ICH6R: 2652h
ICH6-M: 2653h
No
04h
0000h
–
03h
–
05h
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
SATA Controller Registers (D31:F2)
RO, R/W
16 bits
RO
16 bit
Core
457