NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 479

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

12.1.39
.
12.1.40
.
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
SIR84—SATA Indexed Registers Index 84h
(SATA Initialization Register 84h)
Address Offset:
Default Value:
ATC—APM Trapping Control Register (SATA–D31:F2)
Address Offset:
Default Value:
31:6
Bit
5:0
Bit
7:4
3
2
1
0
Reserved.
BIOS programs this field to 101101b.
Reserved
Secondary Slave Trap (SST) — R/W. This bit enables trapping and SMI# assertion on legacy I/O
accesses to 170h–177h and 376h. The active device on the secondary interface must be device 1
for the trap and/or SMI# to occur.
Secondary Master Trap (SPT) — R/W. This bit enables trapping and SMI# assertion on legacy I/O
accesses to 170h–177h and 376h. The active device on the secondary interface must be device 0
for the trap and/or SMI# to occur.
Primary Slave Trap (PST) — R/W. This bit enables trapping and SMI# assertion on legacy I/O
accesses to 1F0h–1F7h and 3F6h. The active device on the primary interface must be device 1 for
the trap and/or SMI# to occur.
Primary Master Trap (PMT) — R/W. This bit enables trapping and SMI# assertion on legacy I/O
accesses to 1F0h–1F7h and 3F6h. The active device on the primary interface must be device 0 for
the trap and/or SMI# to occur.
Index 84h - 87h
0000001Bh
C0h
00h
Description
Description
Attribute:
Size:
Attribute:
Size:
SATA Controller Registers (D31:F2)
R/W
32 bits
R/W
8 bits
479