NH82801FBM S L89K Intel, NH82801FBM S L89K Datasheet - Page 556

• Manufacturer Part Number: NH82801FBM S L89K
• Manufacturer: Intel

Specifications of NH82801FBM S L89K

• Lead Free Status / RoHS Status: Compliant

EHCI Controller Registers (D29:F7)
14.2.2.9
556
PORTSC—Port N Status and Control Register
Offset:
Attribute:
Default Value:
A host controller must implement one or more port registers. Software uses the N_Port information
from the Structural Parameters Register to determine how many ports need to be serviced. All ports
have the structure defined below. Software must not write to unreported Port Status and Control
Registers.
This register is in the suspend power well. It is only reset by hardware when the suspend power is
initially applied or in response to a host controller reset. The initial conditions of a port are:
When a device is attached, the port state transitions to the attached state and system software will
process this as with any status change notification. Refer to Section 4 of the EHCI specification for
operational requirements for how change events interact with port suspend mode.
•
•
31:23
Bit
22
21
20
No device connected
Port disabled.
Reserved. These bits are reserved for future use and will return a value of 0’s when read.
Wake on Overcurrent Enable (WKOC_E) — R/W.
0 = Disable. (Default)
1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power
Wake on Disconnect Enable (WKDSCNNT_E) — R/W.
0 = Disable. (Default)
1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power
Wake on Connect Enable (WKCNNT_E) — R/W.
0 = Disable. (Default)
1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power
Management Control/Status Register (offset 54, bit 15) when the overcurrent Active bit (bit 4 of
this register) is set.
Management Control/Status Register (offset 54, bit 15) when the Current Connect Status
changes from connected to disconnected (i.e., bit 0 of this register changes from 1 to 0).
Management Control/Status Register (offset 54, bit 15) when the Current Connect Status
changes from disconnected to connected (i.e., bit 0 of this register changes from 0 to 1).
Port 0: MEM_BASE + 64
Port 1: MEM_BASE + 68
Port 2: MEM_BASE + 6C
Port 3: MEM_BASE + 70
Port 4: MEM_BASE + 74
Port 5: MEM_BASE + 78
Port 6: MEM_BASE + 7C
Port 7: MEM_BASE + 80
R/W, R/WC, RO
00003000h
–
–
–
–
–
–
Intel
–
–
67h
6Bh
73h
77h
7Bh
83h
6Fh
7Fh
Description
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Size:
32 bits