DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 97

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
Table 3.3
Note: No FPU error occurs in the SH2A-FPU.
3.3.3
Information is transferred between the FPU and CPU via FPUL. FPUL is a 32-bit system register
that is accessed from the CPU side by means of LDS and STS instructions. For example, to
convert the integer stored in general register R1 to a single-precision floating-point number, the
processing flow is as follows:
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
17 to 12
11 to 7
6 to 2
1
0
Field Name
Cause
Enable
Flag
R1 → (LDS instruction) → FPUL → (single-precision FLOAT instruction) → FR1
Floating-Point Communication Register (FPUL)
FPU exception
cause field
FPU exception
enable field
FPU exception flag
field
Bit Name
Cause
Enable
Flag
RM1
RM0
Bit Allocation for FPU Exception Handling
Initial
Value
All 0
All 0
All 0
0
1
FPU
Error (E)
Bit 17
None
None
R/W
R/W
R/W
R/W
R/W
R/W
Invalid
Operation (V)
Bit 16
Bit 11
Bit 6
Description
FPU Exception Cause Field
FPU Exception Enable Field
FPU Exception Flag Field
Each time floating-point operation instruction is
executed, the FPU exception cause field is cleared to 0
first. When an FPU exception on floating-point
operation occurs, the bits corresponding to the FPU
exception cause field and FPU exception flag field are
set to 1. The FPU exception flag field remains set to 1
until it is cleared to 0 by software.
As the bits corresponding to FPU exception enable
filed are sets to 1, FPU exception processing occurs.
For bit allocations of each field, see table 3.3.
Rounding Mode
These bits select the rounding mode.
00: Round to Nearest
01: Round to Zero
10: Reserved
11: Reserved
Division
by Zero (Z)
Bit 15
Bit 10
Bit 5
Overflow
(O)
Bit 14
Bit 9
Bit 4
Section 3 Floating-Point Unit (FPU)
Underflow
(U)
Bit 13
Bit 8
Bit 3
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Inexact
(I)
Bit 12
Bit 7
Bit 2