DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 178

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 6 Interrupt Controller (INTC)
Notes: m1 to m4 are the number of states needed for the following memory accesses.
Page 150 of 1190
Item
Interrupt
response
time
m1: Vector address read (longword read)
m2: SR save (longword write)
m3: PC save (longword write)
m4: Banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored from the
1. In the case of m1 = m2 = m3 = m4 = 1 Icyc.
2. In the case of Iφ:Bφ:Pφ = 120:60:30 [MHz].
No
register
banking
Register
banking
without
register
bank
overflow
Register
banking
with
register
bank
overflow
stack.
Min.
Max.
Min.
Max.
Min.
Max.
NMI
5 Icyc +
2 Bcyc +
1 Pcyc +
m1 + m2
6 Icyc +
2 Bcyc +
1 Pcyc +
2 (m1 + m2)
+ m3
⎯
⎯
⎯
⎯
User Break H-UDI
6 Icyc +
m1 + m2
7 Icyc +
2 (m1 + m2)
+ m3
⎯
⎯
⎯
⎯
Number of States
5 Icyc +
1 Pcyc +
m1 + m2
6 Icyc +
1 Pcyc +
2 (m1 + m2)
+ m3
5 Icyc +
1 Pcyc +
m1 + m2
14 Icyc +
1 Pcyc +
m1 + m2
5 Icyc +
1 Pcyc +
m1 + m2
5 Icyc +
1 Pcyc +
m1 + m2 +
19 (m4)
IRQ, PINT
5 Icyc +
3 Bcyc +
1 Pcyc +
m1 + m2
6 Icyc +
3 Bcyc +
1 Pcyc +
2 (m1 + m2)
+ m3
5 Icyc +
3 Bcyc +
1 Pcyc +
m1 + m2
14 Icyc +
3 Bcyc +
1 Pcyc +
m1 + m2
5 Icyc +
3 Bcyc +
1 Pcyc +
m1 + m2
5 Icyc +
3 Bcyc +
1 Pcyc +
m1 + m2 +
19 (m4)
Peripheral
Module
5 Icyc +
1 Bcyc +
1 Pcyc +
m1 + m2
6 Icyc +
1 Bcyc +
1 Pcyc +
2 (m1 + m2)
+ m3
5 Icyc +
1 Bcyc +
1 Pcyc +
m1 + m2
14 Icyc +
1 Bcyc +
1 Pcyc +
m1 + m2
5 Icyc +
1 Bcyc +
1 Pcyc +
m1 + m2
5 Icyc +
1 Bcyc +
1 Pcyc +
m1 + m2 +
19 (m4)
R01UH0026EJ0300 Rev. 3.00
Remarks
120-MHz operation*
0.067 to 0.142 μs
120-MHz operation*
0.100 to 0.175 μs
120-MHz operation*
0.092 to 0.142 μs
120-MHz operation*
0.167 to 0.217 μs
120-MHz operation*
0.092 to 0.142 μs
120-MHz operation*
0.245 to 0.300 μs
SH7201 Group
Sep 24, 2010
1
1
1
1
1
1
*
*
*
*
*
*
2
2
2
2
2
2
:
:
:
:
:
: