DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 378

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 11 Direct Memory Access Controller (DMAC)
11.5.3
The form in which the DMA end signal (DTENDm) is output differs with the setting of the DMA
end signal output control bit (DTCM) in the DMA mode register (DMMODn) for the
corresponding channel.
• When DTCM is set to "00", output of the DTEND signal is not valid so the signal remains
• When DTCM is set to "01", the DTEND signal becomes active (low) one cycle after the start
• When DTCM is set to "10", the DTEND signal becomes active for one cycle after the write
• When DTCM is set to "11", the DTEND signal becomes active for one clock cycle at the same
Output of the DTEND signal is not valid in the case of DMA requests from external peripheral
circuits, so the signal remains fixed to "H" regardless of the setting of this bit.
Charts of the timing of DMA end signal output are given in figure 11.5.
Note: The BSC is provided with a write buffer. Writing data to this buffer while writing to the
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fixed at the "H" level when and after the DMA transfer ends.
of the read cycle immediately before the end of DMA transfer (the read cycle for the last data
transfer).
cycle immediately before the end of DMA transfer (the write cycle for the last data transfer).
time as the DMA transfer end interrupt is generated.
external devices stops bus access in the chip. Because of this, in DMA transfer to or from
external devices, the DTEND signal become disabled ("H") before the end of external bus
access. In this case the DTEND signal is not synchronized with the external bus access.
DMA End Signal Output
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010