DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 1062

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 28 List of Registers
28.1
Entries under Access Size indicate numbers of bits.
Note: Access to undefined or reserved addresses is prohibited. Since operation or continued
Page 1034 of 1190
Register Name
Bus monitor enable register
Bus monitor status register 1
Bus monitor status register 2
Bus error control register
CS0 control register
CS0 recovery cycle setting register
CS1 control register
CS1 recovery cycle setting register
CS2 control register
CS2 recovery cycle setting register
CS3 control register
CS3 recovery cycle setting register
CS4 control register
CS4 recovery cycle setting register
CS5 control register
CS5 recovery cycle setting register
CS6 control register
CS6 recovery cycle setting register
SDRAMC0 control register
SDRAMC1 control register
CS0 mode register
CS0 wait control register 1
CS0 wait control register 2
CS1 mode register
CS1 wait control register 1
CS1 wait control register 2
CS2 mode register
CS2 wait control register 1
CS2 wait control register 2
operation is not guaranteed when these registers are accessed, do not attempt such access.
Register Addresses (Address Order)
Abbreviation
SYCBEEN
SYCBESTS1
SYCBESTS2
SYCBESW
CS0CNT
CS0REC
CS1CNT
CS1REC
CS2CNT
CS2REC
CS3CNT
CS3REC
CS4CNT
CS4REC
CS5CNT
CS5REC
CS6CNT
CS6REC
SDC0CNT
SDC1CNT
CSMOD0
CS1WCNT0
CS2WCNT0
CSMOD1
CS1WCNT1
CS2WCNT1
CSMOD2
CS1WCNT2
CS2WCNT2
Number
of Bits
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Address
H'FF400000
H'FF400004
H'FF400008
H'FF40000C
H'FF420000
H'FF420008
H'FF420010
H'FF420018
H'FF420020
H'FF420028
H'FF420030
H'FF420038
H'FF420040
H'FF420048
H'FF420050
H'FF420058
H'FF420060
H'FF420068
H'FF420100
H'FF420110
H'FF421000
H'FF421004
H'FF421008
H'FF421010
H'FF421014
H'FF421018
H'FF421020
H'FF421024
H'FF421028
R01UH0026EJ0300 Rev. 3.00
Module
Bus Monitor
BSC
SH7201 Group
Sep 24, 2010
Access
Size
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32