DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 756

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 16 Serial Communication Interface with FIFO (SCIF)
16.6.6
The SCIF operates on a base clock with a frequency of 16 times the transfer rate. In reception, the
SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock.
Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in
figure 16.17.
The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.
Equation 1:
Where: M: Receive margin (%)
From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2.
Equation 2:
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Page 728 of 1190
Base clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
M = (0.5 -
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
When D = 0.5 and F = 0:
M = (0.5 - 1/(2
= 46.875%
Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)
Figure 16.17 Receive Data Sampling Timing in Asynchronous Mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
2N
1
8 clocks
Start bit
) - (L - 0.5) F -
16))
16 clocks
100%
–7.5 clocks
D - 0.5
N
(1 + F)
+7.5 clocks
100 %
D0
6 7 8 9 10 11 12 13 14 15
R01UH0026EJ0300 Rev. 3.00
0 1 2 3 4 5
SH7201 Group
Sep 24, 2010
D1