DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 1193

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
5.7.6 FPU Exceptions
5.9 Stack Status after Exception
Handling Ends
Table 5.12 Stack Status After
Exception Handling Ends
6.5 Interrupt Exception Handling
Vector Table and Priority
Table 6.4 Interrupt Exception
Handling Vectors and Priorities
6.8 Register Banks
Figure 6.10 Overview of Register
Bank Configuration
Item
Page
111
113
137 to
145
154
Revision (See Manual for Details)
Description amended
The FPU exception flag field (Flag) of FPSCR is
always updated regardless of whether or not an FPU
exception handling has been accepted, and remains
set until explicitly cleared by the user through an
instruction. The FPU exception source field (Cause) of
FPSCR changes each time a floating-point operation
instruction is executed.
When the V bit in the FPU exception enable field
(Enable) of FPSCR is set and the QIS bit in FPSCR is
also set, FPU exception handling is generated when
qNAN or ±∞ is input to a floating point operation
instruction source.
Table amended
Table amended
Figure amended
Interrupt Source
Exception Type
Integer division exception
Interrupt generated
RESBANK
instruction
(restore)
(save)
Vector
Interrupt Vector
Vector Table
Address Offset
Register banks
Stack Status
SP
MACH
MACL
GBR
VTO
R14
PR
R0
R1
:
:
Start address of relevant
integer division instruction
SR
Interrupt
Priority
(Initial
Value)
Main Revisions for This Edition
Corresponding
IPR (Bit)
Bank 0
Bank 1
Page 1165 of 1190
....
32 bits
32 bits
Bank 14
IPR
Setting
Unit
Internal
Priority
Default
Priority