DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 910

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 20 A/D Converter (ADC)
20.3.2
ADCSR is a 16-bit readable/writable register that selects the mode, controls the A/D converter,
and enables or disables starting of A/D conversion by external trigger input.
ADCSR is initialized to H'0040 by a power-on reset as well as in deep standby mode, software
standby mode or module standby mode.
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Initial value:
Bit
15
14
Note:
R/W:
Bit:
*
A/D Control/Status Register (ADCSR)
Only 0 can be written to clear the flag after 1 is read.
R/(W)* R/W
Bit Name
ADF
ADIE
ADF ADIE ADST
15
0
14
0
R/W
13
0
Initial
Value
0
0
12
—
R
0
R/W
11
R/W
R/(W)*
R/W
0
R/W
TRGS[3:0]
10
0
1
Description
A/D End Flag
Status flag indicating the end of A/D conversion.
[Clearing conditions]
•
•
[Setting conditions]
•
•
•
A/D Interrupt Enable
Enables or disables the interrupt (ADI) requested at
the end of A/D conversion. Set the ADIE bit while A/D
conversion is not being made.
0: A/D end interrupt request (ADI) is disabled
1: A/D end interrupt request (ADI) is enabled
R/W
0
9
Cleared by reading ADF while ADF = 1, then
writing 0 to ADF
Cleared when DMAC is activated by ADI interrupt
and ADDR is read
A/D conversion ends in single mode
A/D conversion ends for the selected channels in
multi mode
A/D conversion ends for the selected channels in
scan mode
R/W
8
0
R/W
CKS[1:0]
7
0
R/W
6
1
R/W
5
0
MDS[2:0]
R/W
4
0
R01UH0026EJ0300 Rev. 3.00
R/W
3
0
R/W
2
0
SH7201 Group
CH[2:0]
R/W
Sep 24, 2010
1
0
R/W
0
0