DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 226

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 8 Cache
8.4.4
1. Programs that access memory-mapped cache of the operand cache should be placed in a cache-
2. Rewriting the address array contents so that two or more ways are hit simultaneously is
3. Memory-mapped cache can be accessed only by the CPU and not by the DMAC. Registers can
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disabled space. Programs that access memory-mapped cache of the instruction cache should be
placed in a cache-disabled space, and in each of the beginning and the end of that, two or more
read accesses to on-chip peripheral modules or external address space (cache-disabled address)
should be executed.
prohibited. Operation is not guaranteed if the address array contents are changed so that two or
more ways are hit simultaneously.
be accessed by the CPU and the DMAC.
Notes
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010