DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 231

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
9.3
9.3.1
In the architecture, this LSI has a 32-bit address space, which is divided into cache-enabled,
cache-disabled, and on-chip spaces (on-chip RAM, on-chip peripheral modules, and reserved
areas) according to the upper bits of the address.
External address spaces CS5 to CS0 are cache-enabled when internal address A29 = 0 and cache-
disabled when A29 = 1. The CS6 space is always cache-disabled.
The kind of memory to be connected and the data bus width are specified independently for each
partial space. The address map for the external address space is listed below.
Table 9.2
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Internal Address
H'00000000 to H'03FFFFFF
H'04000000 to H'07FFFFFF
H'08000000 to H'0BFFFFFF
H'0C000000 to H'0FFFFFFF
H'10000000 to H'13FFFFFF
H'14000000 to H'17FFFFFF
H'18000000 to H'1BFFFFFF
H'1C000000 to H'1FFFFFFF
H'20000000 to H'23FFFFFF
H'24000000 to H'27FFFFFF
H'28000000 to H'2BFFFFFF
H'2C000000 to H'2FFFFFFF
H'30000000 to H'33FFFFFF
H'34000000 to H'37FFFFFF
H'38000000 to H'3BFFFFFF
H'3C000000 to H'3FFFFFFF
Area Overview
Address Map
Address Map
Space
SDRAM0
SDRAM1
SDRAM0
SDRAM1
CS0
CS1
CS2
CS3
CS4
CS5
CS0
CS1
CS2
CS3
CS4
CS5
Memory to be Connected
Normal space
Normal space
SDRAM
SDRAM
Normal space
Normal space
Normal space
Normal space
Normal space
Normal space
SDRAM
SDRAM
Normal space
Normal space
Normal space
Normal space
Section 9 Bus State Controller (BSC)
Page 203 of 1190
Cache
Cache-
enabled
Cache-
disabled