DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 349

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
9
8
7, 6
Bit Name
SRLOD
DRLOD
⎯
Initial
Value
0
0
All 0
R/W
R/W
R/W
R
Description
DMA Source Address Reload Function Enable
This bit specifies whether or not the source address is
reloaded when the DMA transfer end condition is
detected.
When this bit is cleared to "0", reloading is not
executed.
When this bit is set to "1" and the DMA transfer end
condition is detected, the DMA current source address
register (DMCSADRn) is reloaded with the value of the
DMA reload source address register (DMRSADRn).
0: Source address reload function disabled
1: Source address reload function enabled
DMA Destination Address Reload Function Enable
This bit specifies whether or not the destination
address is reloaded when the DMA transfer end
condition is detected.
When this bit is cleared to "0", reloading is not re-
executed.
When this bit is set to "1" and the DMA transfer end
condition is detected, the DMA current destination
address register (DMCDADRn) is reloaded with the
value of the DMA reload destination address register
(DMRDADRn).
0: Destination address reload function disabled
1: Destination address reload function enabled
Reserved
These bits are always read as 0. The write value
should always be 0.
Section 11 Direct Memory Access Controller (DMAC)
Page 321 of 1190