DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 22

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

17.5
17.6
17.7
Section 18 Serial Sound Interface (SSI)............................................................773
18.1
18.2
18.3
18.4
18.5
Section 19 Controller Area Network (RCAN-ET) ............................................811
19.1
Page xxii of xxviii
17.4.6
17.4.7
17.4.8
Interrupt Requests ............................................................................................................. 766
Bit Synchronous Circuit.................................................................................................... 767
Usage Note........................................................................................................................ 770
17.7.1
17.7.2
17.7.3
17.7.4
17.7.5
17.7.6
Features............................................................................................................................. 773
Input/Output Pins.............................................................................................................. 775
Register Description ......................................................................................................... 776
18.3.1
18.3.2
18.3.3
18.3.4
Operation Description....................................................................................................... 789
18.4.1
18.4.2
18.4.3
18.4.4
18.4.5
18.4.6
18.4.7
Usage Notes ...................................................................................................................... 809
18.5.1
18.5.2
18.5.3
Summary........................................................................................................................... 811
19.1.1
19.1.2
19.1.3
19.1.4
Clocked Synchronous Serial Format................................................................. 757
Noise Filter ....................................................................................................... 761
Example of Use................................................................................................. 762
Issuance of Stop Condition and Start Condition (Retransmission)................... 770
Note on Setting for Multi-Master Operation..................................................... 770
Note on Master Receive Mode ......................................................................... 770
Note on Setting ACKBT in Master Receive Mode........................................... 770
Note on the States of Bits MST and TRN when Arbitration is Lost................. 771
Note on IICRST and BBSY bits ....................................................................... 771
Control Register (SSICR) ................................................................................. 777
Status Register (SSISR) .................................................................................... 783
Transmit Data Register (SSITDR).................................................................... 788
Receive Data Register (SSIRDR) ..................................................................... 788
Bus Format........................................................................................................ 789
Non-Compressed Modes................................................................................... 790
Operation Modes............................................................................................... 800
Transmit Operation ........................................................................................... 801
Receive Operation............................................................................................. 804
Temporary Stop and Restart Procedures in Transmit Mode ............................. 807
Serial Bit Clock Control ................................................................................... 808
Limitations from Overflow during Receive DMA Operation........................... 809
Note on Using Oversample Clock .................................................................... 809
Restriction on Stopping Clock Supply.............................................................. 809
Overview........................................................................................................... 811
Scope ................................................................................................................ 811
Audience ........................................................................................................... 811
References......................................................................................................... 812
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010