DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 356

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 11 Direct Memory Access Controller (DMAC)
Page 328 of 1190
Bit
16
Bit Name
DREQ
Initial
Value
0
R/W
R/W
Description
(b) When a source other than the software trigger is
•
•
Note:
selected (DCTG = "000000") by the DMA request
source selection bits (DCTG) and a level sense
has been selected
Condition for setting to "1"
This bit is set to "1" when the DMA request input
level matches that specified in the input sense
selection bits (STRG), i.e. when a DMA request
exists.
Condition for clearing to "0"
This bit is cleared to "0" when the level specified by
the input sense selection bits (STRG) and the level
on the DMA request input do not match, i.e. when
there is no DMA request.
The DMA request is not retained if it disappears
before being accepted; that is, the DMA request bit
(DREQ) is cleared to "0". To use the DREQ bit with
a level sense, continue the DMA request level until
the request has been accepted.
When a requesting source other than the
software trigger is selected, do not write "1" to
the DMA request bit (DREQ). If "1" is written to
this bit, operation is not guaranteed.
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010