DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 12

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

6.4
6.5
6.6
6.7
6.8
6.9
6.10
Section 7 User Break Controller (UBC)............................................................161
7.1
7.2
7.3
Page xii of xxviii
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
6.3.12
6.3.13
Interrupt Sources............................................................................................................... 133
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
Interrupt Exception Handling Vector Table and Priority.................................................. 136
Operation .......................................................................................................................... 146
6.6.1
6.6.2
Interrupt Response Time................................................................................................... 149
Register Banks .................................................................................................................. 154
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
Data Transfer with Interrupt Request Signals................................................................... 159
6.9.1
6.9.2
Usage Note........................................................................................................................ 160
6.10.1
Features............................................................................................................................. 161
Input/Output Pin ............................................................................................................... 163
Register Descriptions........................................................................................................ 163
7.3.1
7.3.2
PINT Interrupt Enable Register (PINTER)....................................................... 125
PINT Interrupt Request Register (PIRR) .......................................................... 126
Bank Control Register (IBCR).......................................................................... 127
Bank Number Register (IBNR) ........................................................................ 128
DMA Transfer Request Enable Register 0 (DREQER0) .................................. 129
DMA Transfer Request Enable Register 1 (DREQER1) .................................. 130
DMA Transfer Request Enable Register 2 (DREQER2) .................................. 131
DMA Transfer Request Enable Register 3 (DREQER3) .................................. 132
NMI Interrupt.................................................................................................... 133
User Break Interrupt ......................................................................................... 133
H-UDI Interrupt ................................................................................................ 133
IRQ Interrupts................................................................................................... 134
PINT Interrupts ................................................................................................. 135
On-Chip Peripheral Module Interrupts ............................................................. 135
Interrupt Operation Sequence ........................................................................... 146
Stack after Interrupt Exception Handling ......................................................... 148
Register Banks and Bank Control Registers ..................................................... 155
Bank Save and Restore Operations................................................................... 155
Save and Restore Operations after Saving to All Banks................................... 157
Register Bank Exception................................................................................... 158
Register Bank Error Exception Handling ......................................................... 158
Handling Interrupt Request Signals as Sources for CPU Interrupt
but not DMAC Activation ................................................................................ 159
Handling Interrupt Request Signals as Sources for DMAC Activation
but not CPU Interrupt ....................................................................................... 159
Timing to Clear an Interrupt Source ................................................................. 160
Break Address Register (BAR)......................................................................... 164
Break Address Mask Register (BAMR) ........................................................... 165
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010