DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 863

IC SH7201 MPU ROMLESS 176LQFP

DS72011RB120FPV

Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet

Specifications of DS72011RB120FPV

Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
SH7201 Group
Bit 11: Reserved. The written value should always be '0' and the returned value is '0'.
Bits 10 to 8 — Time Segment 2 (TSG2[2:0] = BCR1[10:8]): These bits are used to set the
segment TSEG2 ( = PHSEG2) to compensate for edges on the CAN Bus with a negative phase
error. A value from 2 to 8 time quanta can be set as shown below.
Bits 7 and 6: Reserved. The written value should always be '0' and the returned value is '0'.
Bits 5 and 4 - ReSynchronisation Jump Width (SJW[1:0] = BCR0[5:4]): These bits set the
synchronisation jump width.
Bits 3 to 1: Reserved. The written value should always be '0' and the returned value is '0'.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit 10:
TSG2[2]
0
0
0
0
1
1
1
1
Bit 5:
SJW[1]
0
0
1
1
Bit 9:
TSG2[1]
0
0
1
1
0
0
1
1
Bit 4:
SJW[0]
0
1
0
1
Bit 8:
TSG2[0] Description
0
1
0
1
0
1
0
1
Setting prohibited (Initial value)
PHSEG2 = 2 time quanta (conditionally prohibited) See the table
below for TSG1 and TSG2 setting.
PHSEG2 = 3 time quanta
PHSEG2 = 4 time quanta
PHSEG2 = 5 time quanta
PHSEG2 = 6 time quanta
PHSEG2 = 7 time quanta
PHSEG2 = 8 time quanta
Description
Synchronisation Jump width = 1 time quantum (Initial value)
Synchronisation Jump width = 2 time quanta
Synchronisation Jump width = 3 time quanta
Synchronisation Jump width = 4 time quanta
Section 19 Controller Area Network (RCAN-ET)
Page 835 of 1190

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