DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 162

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
Section 6 Interrupt Controller (INTC)
6.4.4
IRQ Interrupts
IRQ interrupts are input from pins IRQ7 to IRQ0. As regard to the setting method of pins IRQ7 to
IRQ0, see section 23, Pin Function Controller (PFC). For the IRQ interrupts, low-level, falling-
edge, rising-edge, or both-edge detection can be selected individually for each pin by the IRQ
sense select bits (IRQ71S to IRQ01S and IRQ70S to IRQ00S) in interrupt control register 1
(ICR1). The priority level can be set individually in a range from 0 to 15 for each pin by interrupt
priority registers 01 and 02 (IPR01 and IPR02).
When using low-level sensing for IRQ interrupts, an interrupt request signal is sent to the INTC
while the IRQ7 to IRQ0 pins are low. An interrupt request signal is stopped being sent to the
INTC when the IRQ7 to IRQ0 pins are driven high. The status of the interrupt requests can be
checked by reading the IRQ interrupt request bits (IRQ7F to IRQ0F) in the IRQ interrupt request
register (IRQRR).
When using edge-sensing for IRQ interrupts, an interrupt request is detected due to change of the
IRQ7 to IRQ0 pin states, and an interrupt request signal is sent to the INTC. The result of IRQ
interrupt request detection is retained until that interrupt request is accepted. Whether IRQ
interrupt requests have been detected or not can be checked by reading the IRQ7F to IRQ0F bits in
IRQRR. Writing 0 to these bits after reading them as 1 clears the result of IRQ interrupt request
detection.
The IRQ interrupt exception handling sets the I3 to I0 bits in SR to the priority level of the
accepted IRQ interrupt.
When restoring from the service routine of IRQ interrupt exception handling, execute the RTE
instruction after an interrupt request has been cleared in the IRQ interrupt request register
(IRQRR).
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Sep 24, 2010