DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 426

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.21 TIORL_0 (Channel 0)
[Legend]
X:
Notes: 1. After power-on reset, 0 is output until TIOR is set.
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Bit 3
IOC3
0
1
Don't care
2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this
Bit 2
IOC2
0
1
0
1
setting is invalid and input capture/output compare is not generated.
Bit 1
IOC1
0
1
0
1
0
1
X
Bit 0
IOC0
0
1
0
1
0
1
0
1
0
1
X
X
TGRC_0
Function
Output
compare
register*
Input capture
register*
2
2
TIOC0C Pin Function
Output retained*
Initial output is 0
0 output at compare match
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
Output retained
Initial output is 1
0 output at compare match
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
Description
1
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010