DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 739

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
Figure 16.3 shows a sample flowchart for initializing the SCIF.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
After reading ER, DR, and BRK flags
Clear TE and RE bits in SCSCR to 0
in SCFSR, and each flag in SCLSR,
Set RTRG[1:0] and TTRG[1:0] bits
Set TE and RE bits in SCSCR to 1,
Set data transfer format in SCSMR
PFC setting for external pins used
in SCSCR (leaving TIE, RIE, TE,
and set TIE, RIE, and REIE bits
in SCFCR, and clear TFRST
Set TFRST and RFRST bits
and RE bits cleared to 0)
Figure 16.3 Sample Flowchart for SCIF Initialization
and RFRST bits to 0
write 0 to clear them
Set value in SCBRR
Start of initialization
End of initialization
Set CKE[1:0] bits
SCK, TxD, RxD
in SCFCR to 1
[1]
[2]
[3]
[4]
[5]
Section 16 Serial Communication Interface with FIFO (SCIF)
[1]
[2]
[3]
[4]
[5]
Set the clock selection in SCSCR.
Be sure to clear bits TIE, RIE, TE,
and RE to 0.
Set the data transfer format in
SCSMR.
Write a value corresponding to the
bit rate into SCBRR. (Not
necessary if an external clock is
used.)
Sets PFC for external pins used.
Set as RxD input at reciving and
TxD at transmission.
However, no setting for SCK pin is
required when CKE[1:0] is 00.
Set the TE bit or RE bit in SCSCR
to 1. Also set the RIE, REIE, and
TIE bits. Setting the TE and RE bits
enables the TxD and RxD pins to
be used.
When transmitting, the SCIF will go
to the mark state; when receiving,
it will go to the idle state, waiting for
a start bit.
When the intrnal clock output is
selected, a clock starts to be output
from the SCK pin at this point.
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