DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 791
![IC SH7201 MPU ROMLESS 176LQFP](/photos/28/61/286154/176-lqfp_sml.jpg)
DS72011RB120FPV
Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet
1.R0K572011S000BE.pdf
(1222 pages)
Specifications of DS72011RB120FPV
Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 791 of 1222
- Download datasheet (8Mb)
SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
No
No
No
Clear ACKBT in ICIER to 0
Clear RCVD in ICCR1 to 0
Write 0 to BBSY and SCP
Set ACKBT in ICIER to 1
Clear MST in ICCR1 to 0
Clear TRS in ICCR1 to 0
Set RCVD in ICCR1 to 1
Master receive mode
Dummy-read ICDRR
Read RDRF in ICSR
Read RDRF in ICSR
Clear TEND in ICSR
Clear TDRE in ICSR
Clear STOP in ICSR
Read STOP in ICSR
Read ICDRR
Read ICDRR
Read ICDRR
Last receive
RDRF = 1 ?
STOP = 1 ?
RDRF=1 ?
Figure 17.19 Sample Flowchart for Master Receive Mode
- 1?
End
Yes
Yes
Yes
No
Yes
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[1] Clear TEND, select master receive mode,
[2] Set acknowledge to the transmit device. *
[3] Dummy-read ICDDR. *
[4] Wait for 1 byte to be received
[5] Check whether it is the (last receive - 1).
[6] Read the receive data.
[7] Set acknowledge of the final byte.
[8] Read the (final byte - 1) of received data.
[9] Wait for the last byte to be receive.
[10] Clear the STOP flag.
[11] Issue the stop condition.
[12] Wait for the creation of stop condition.
[13] Read the last byte of receive data.
[14] Clear RCVD.
[15] Set slave receive mode.
Notes: * Make sure that no interrupt will be generated during
and then clear TDRE. *
Disable continuous reception (RCVD = 1).
steps [1] to [3].
When the size of receive data is only one byte in
reception, steps [2] to [6] are skipped after step [1],
before jumping to step [7].
The step [8] is dummy-read in ICDRR.
Section 17 I
2
C Bus Interface 3 (IIC3)
Page 763 of 1190
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