DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 159

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
6.3.12
DMA transfer request enable register 2 (DREQER2) is an 8-bit readable/writable register that
enables/disables the SCIF (channels 4 to 7) DMA transfer requests, and enables/disables CPU
interrupt requests.
DMA transfer request enable register 2 is initialized by a power-on reset or in deep standby mode.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
7
6
5
4
3
2
1
0
Bit Name
SCIF 7ch TX
SCIF 7ch RX
SCIF 6ch TX
SCIF 6ch RX
SCIF 5ch TX
SCIF 5ch RX
SCIF 4ch TX
SCIF 4ch RX
DMA Transfer Request Enable Register 2 (DREQER2)
Initial value:
Initial
Value
0
0
0
0
0
0
0
0
R/W:
Bit:
7ch TX
SCIF
R/W
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
7ch RX
SCIF
R/W
0
6
Description
DMA Transfer Request Enable Bits
These bits enable/disable DMA transfer requests, and
enable/disable CPU interrupt requests.
0: DMA transfer request disabled, CPU interrupt
1: DMA transfer request enabled, CPU interrupt request
6ch TX
SCIF
R/W
0
5
request enabled
disabled
6ch RX
SCIF
R/W
0
4
5ch TX
SCIF
R/W
0
3
5ch RX
SCIF
R/W
0
2
4ch TX
SCIF
R/W
1
0
Section 6 Interrupt Controller (INTC)
4ch RX
SCIF
R/W
0
0
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