DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 316

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 10 Bus Monitor
Table 10.2 Bus Space and Slave Bus
Notes: 1. This means bus spaces in the slave bus space other than those for the external bus
Page 288 of 1190
Bit
9, 8
7 to 0
Address
H'0000 0000 to H'4FFF FFFF
H'5000 0000 to H'E800 FFFF
H'E801 0000 to H'EFFF FFFF
H'F000 0000 to H'F1FF FFFF
H'F200 0000 to H'F5FF FFFF
H'F600 0000 to H'FF3F FFFF
H'FF40 0000 to H'FF5F FFFF
H'FF60 0000 to H'FFF7 FFFF
H'FFF8 0000 to H'FFF8 7FFF
H'FFF8 8000 to H'FFFB FFFF
H'FFFC 0000 to H'FFFF FFFF
2. An illegal address access error does not occur.
Bit Name
PMST[1:0]
⎯
and peripheral buses (1) and (2).
Initial
Value
00
All 0
Bus Space
External bus space
Reserved
Reserved
Address array space in cache
Reserved
Reserved
On-chip peripheral module (1)
Reserved
On-chip RAM
Reserved
On-chip peripheral module (2)
R/W
R
R
Description
Bus Master
These bits indicate the bus master that accessed
peripheral bus (1) when the first bus error occurred.
00: CPU
01: DMAC (destination side)
10: Setting prohibited
11: DMAC (source side)
Reserved
These bits are always read as 0. The write value
should always be 0.
Slave Bus
External bus
(Others*
(Others*
⎯*
⎯*
(Others*
Peripheral bus (1)
(Others*
⎯*
⎯*
Peripheral bus (2)
2
2
2
2
R01UH0026EJ0300 Rev. 3.00
1
1
1
1
)
)
)
)
SH7201 Group
Sep 24, 2010