DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 270

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
4. Tdw1 to Tdwn (Write Data Output Delay Cycle)
5. Tpw1 to Tpwn (Page Read Cycle Wait, Page Write Cycle Wait)
6. Tend/Tdw1 to Tdwn (Wait End Cycle/Write Data Output Delay Cycle)
7. Tn1 to Tnm (CS Delay Cycle)
8. Trd (Final Read Data Sample Cycle)
(3)
The external wait signal (WAIT) can be used to extend the wait cycle duration beyond the value
specified by the cycle wait (CSRWAIT, CSWWAIT) or page access cycle wait (CSPRWAIT,
CSPWWAIT) settings in the CSn wait control register (CSWCNTn). If external wait enable
(EWENB = 1) has been selected, wait cycles are inserted for as long as the WAIT signal remains
low level. The WAIT signal is disabled if external wait disable (EWENB = 0) has been selected.
Note that the wait cycles specified by the settings of the CSn wait control register (CSWCNTn)
are inserted regardless of the state of the WAIT signal.
(a)
The WAIT signal is sampled all the time and its result is reflected two cycles later. Thus, when the
WAIT signal is low two cycles before the end of the wait cycles, external cycles are inserted.
After the WAIT signal has gone high, the wait cycles end two cycles later.
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In write access write data output delay cycles are inserted between the wait end cycle and the
following page access if the write data output delay wait setting is other than 0. Assertion of
the address and output data is extended for the duration of this interval. Also, the WR signal is
negated (high level).
In page access the page read cycle wait and page write cycle wait settings are used in place of
the read cycle wait and write cycle wait settings for the second and subsequent bus cycles. The
WR assert wait setting works the same as during the first bus cycle. The RD assert wait setting
operates differently depending on the page read access mode (PRMOD) setting value.
PRMOD = 0: RD assert wait setting operates identically to first bus cycle.
PRMOD = 1: RD assert wait setting is invalid. Operation is the same as an RD assert wait
These operate the same as during the first access (3 and 4 above).
These are the cycles between the final wait end cycle and when CSn is negated (high level).
The number of CS delay cycles is counted beginning from the wait end cycle.
This is the final sample cycle for read data.
External Wait Function
Normal Read/Write Operation
setting of 0.
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010