DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 113

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
6 to 4
3
2 to 0
Bit Name
IFC[2:0]
RNGS
PFC[2:0]
Initial
Value
000
0
011
R/W
R/W
R/W
R/W
Description
CPU Clock Frequency Division Ratio
These bits specify the frequency division ratio of the
CPU clock with respect to the output frequency of
PLL circuit 1.
000: × 1 time
001: × 1/2 time
010: × 1/3 time
011: × 1/4 time
100: × 1/6 time
101: × 1/8 time
Output Range Select for PLL Circuit 1
When the multiplication ratio for the PLL circuit 1 is
specified to × 3, set this bit according to the output
frequency of the PLL circuit 1.
0: Low frequency mode
1: High frequency mode
Peripheral Clock Frequency Division Ratio
These bits specify the frequency division ratio of the
peripheral clock with respect to the output frequency
of PLL circuit 1.
000: × 1 time
001: × 1/2 time
010: × 1/3 time
011: × 1/4 time
100: × 1/6 time
101: × 1/8 time
110: × 1/12 time
(Output frequency of the PLL circuit 1 is equal to
or smaller than 120 MHz.)
(Multiplication ratio for the PLL circuit 1 is specified
to × 3 and its output frequency exceeds 120 MHz.)
Section 4 Clock Pulse Generator (CPG)
Page 85 of 1190