DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 250

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
Note: Auto-refresh requests are not accepted while multiple read or write accesses are in
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Bit
15 to 12 DREFW
11 to 0
progress, or during a transfer using DMAC, so the auto-refresh interval may become
enlarged in some cases. Set the DRFC bits to an auto-refresh request interval value that
satisfies the auto-refresh interval specification of the SDRAM being used. Furthermore,
make sure to set the auto-refresh request interval to a duration longer than the auto-refresh
cycle.
Bit Name
[3:0]
DRFC
[11:0]
Initial
Value
Undefined R/W
Undefined R/W
R/W
Description
Auto-Refresh Cycle/Self-Refresh Clearing Cycle Count
Setting
These bits specify the number of auto-refresh cycles
and the number of self-refresh clearing cycles. The
DREFW bits can be written to at any time, regardless
of the state of the auto-refresh operation enable
(DRFEN) bit. If auto-refresh is disabled, the value
written to these bits takes effect immediately. If auto-
refresh is enabled, the value written to these bits takes
effect immediately if an auto-refresh cycle is not in
progress. If an auto-refresh cycle is in progress, the
new value takes effect after the cycle completes.
0000: 1 cycle
0001: 2 cycles
0010: 3 cycles
1111: 16 cycles
Auto-Refresh Request Interval Setting
These bits specify the auto-refresh interval. The DRFC
bits can be written to at any time, regardless of the
state of the auto-refresh operation enable (DRFEN) bit.
If auto-refresh is disabled, the value written to these
bits takes effect immediately. If auto-refresh is enabled,
the value written to these bits is reflected in the
operation of the refresh counter from the next auto-
refresh request generated.
000000000000: Setting prohibited
000000000001: 2 cycles
000000000010: 3 cycles
111111111111: 4096 cycles
:
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R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010