DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 1036
![IC SH7201 MPU ROMLESS 176LQFP](/photos/28/61/286154/176-lqfp_sml.jpg)
DS72011RB120FPV
Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet
1.R0K572011S000BE.pdf
(1222 pages)
Specifications of DS72011RB120FPV
Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 25 Power-Down Modes
25.3
25.3.1
(1)
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip modules
continue to run in sleep mode. Clock pulses continue to be output on the CKIO pin.
(2)
Sleep mode is canceled by an interrupt (NMI, H-UDI, IRQ, PINT, and on-chip peripheral
module), a bus error, or a reset (manual reset or power-on reset).
• Canceling with an interrupt
• Canceling with a bus error
• Canceling with a reset
Page 1008 of 1190
When an NMI, H-UDI, IRQ, PINT, or on-chip peripheral module interrupt occurs, sleep mode
is canceled and interrupt exception handling is executed. When the priority level of the
generated interrupt is equal to or lower than the interrupt mask level that is set in the status
register (SR) of the CPU, or the interrupt by the on-chip peripheral module is disabled on the
module side, the interrupt request is not accepted and sleep mode is not canceled.
When a bus error occurs, sleep mode is canceled and bus error exception handling is executed.
Sleep mode is canceled by a power-on reset or a manual reset.
Transition to Sleep Mode
Canceling Sleep Mode
Operation
Sleep Mode
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010
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