DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 1207

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
29.3.1 Clock Timing
Table 29.5 Clock Timing
29.3.3 Bus Timing
Table 29.7 Bus Timing
Figure 29.10 (1) External
Address Space: Basic Bus Timing
(Normal Access, Read/Write
Cycle Wait = 3, CS Assert Wait =
1, Write Data Output Wait = 1,
WR/RD Assert Wait = 2, Write
Data Output Delay Cycles = 0,
Read/Write CS Delay Cycles = 1)
Figure 29.10 (2) External
Address Space: Basic Bus Timing
(Normal Access, Data Recovery
Cycles = 0, Read/Write Cycle Wait
= 1, Read/Write CS Delay Cycles
= 1, Other Wait Settings = 0)
Figure 29.10 (3) External
Address Space: Basic Bus Timing
(Normal Access, Data Recovery
Cycles = 2, Read/Write Cycle Wait
= 1, Read/Write CS Delay Cycles
= 1, Other Wait Settings = 0)
Item
Page
1117
1123
1123
1124
1125
Revision (See Manual for Details)
Table amended
Note amended
Notes: 2. The maximum value (f
Figure and figure title amended
CKIO
Figure added
Figure added
Item
CKIO clock input frequency
CKIO clock input cycle time
CKIO clock input pulse low width
CKIO clock input pulse high width
CKIO clock input rise time
CKIO clock input fall time
CKIO clock output frequency
CKIO clock output cycle time
CKIO clock output pulse low width
CKIO clock output pulse high width
CKIO clock output rise time
CKIO clock output fall time
clock) depends on the number of wait
cycles and the system configuration of
your board.
Tw1
Tw2
Symbol Min.
f
t
t
t
t
t
f
t
t
t
t
t
CK
CKIcyc
CKIL
CKIH
CKIr
CKIf
OP
cyc
CKOL
CKOH
CKOr
CKOf
Tw3
20
16.67
0.4
0.4
⎯
⎯
20
16.67
t
t
⎯
⎯
cyc
cyc
Main Revisions for This Edition
/2 − t
/2 − t
Tend (Trd)
CKOr
CKOf
max
) of Bφ (
Max.
60
50
0.6
0.6
3
3
60
50
⎯
⎯
3
3
Tn1
Page 1179 of 1190
Unit
MHz
ns
t
t
ns
ns
MHz
ns
ns
ns
ns
ns
CKIcyc
CKIcyc
Figure
Figure 29.2
Figure 29.3
Ts
bus