DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 374
![IC SH7201 MPU ROMLESS 176LQFP](/photos/28/61/286154/176-lqfp_sml.jpg)
DS72011RB120FPV
Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet
1.R0K572011S000BE.pdf
(1222 pages)
Specifications of DS72011RB120FPV
Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 374 of 1222
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Section 11 Direct Memory Access Controller (DMAC)
11.4.3
(1)
Initial settings must be made in each of the relevant registers before the DMA transfer enable bit is
set (DEN = "1"). These settings cannot be changed once transfer has started.
An example of DMAC registers that require initial settings is given below.
1. DMA mode register (DMMODn)
2. DMA control register A (DMCNTAn)
3. DMA control register B (DMCNTBn)
4. DMA current source address register (DMCSADRn)
5. DMA reload source address register (DMRSADRn) ⎯ when the reload function is used
6. DMA current destination address register (DMCDADRn)
7. DMA reload destination address register (DMRDADRn) ⎯ when the reload function is used
8. DMA current byte count register (DMCBCTn)
9. DMA reload byte count register (DMRBCTn) ⎯ when the reload function is used
10. DMA interrupt control register (DMICNT) ⎯ when an interrupt is used
11. DMA common interrupt control register (DMICNTA) ⎯ when an interrupt is used
12. DMA transfer enable bit (DEN)
13. DMA activation control register (DMSCNT)
(2)
DMA transfer for a channel is enabled by setting the DMA transfer enable bit (DEN) in DMA
control register B for the channel and the DMAC module activation bit (DMST) in the DMAC
activation register (DMSCNT) to "1".
When multiple DMA transfer requests are present, there is no complex mechanism for the
determination of channel priority. The DMA request that corresponds to the highest priority
channel is simply accepted and DMA transfer on that channel starts.
Whether a DMA request on a given channel is or is not present can be verified by testing the value
of the DMA request bit (DREQ) in DMA control register B (DMCNTBn) for that channel.
When a DMA request is accepted and DMA transfer starts, the DMA arbitration status bit
(DASTS) for the corresponding channel in the DMA arbitration status register (DMASTS) is set
to "1".
Page 346 of 1190
Initial Settings of the DMAC
DMA Activation
DMA Activation
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010
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