DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 13

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

7.4
7.5
Section 8 Cache..................................................................................................181
8.1
8.2
8.3
8.4
Section 9 Bus State Controller (BSC)................................................................199
9.1
9.2
9.3
9.4
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
7.3.3
7.3.4
7.3.5
7.3.6
Operation .......................................................................................................................... 173
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
Usage Notes ...................................................................................................................... 180
Features............................................................................................................................. 181
8.1.1
Register Descriptions ........................................................................................................ 184
8.2.1
8.2.2
Operation .......................................................................................................................... 189
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
Memory-Mapped Cache ................................................................................................... 194
8.4.1
8.4.2
8.4.3
8.4.4
Features............................................................................................................................. 199
Input/Output Pins.............................................................................................................. 201
Area Overview.................................................................................................................. 203
9.3.1
9.3.2
Register Descriptions ........................................................................................................ 205
9.4.1
9.4.2
Break Data Register (BDR) .............................................................................. 166
Break Data Mask Register (BDMR) ................................................................. 167
Break Bus Cycle Register (BBR)...................................................................... 168
Break Control Register (BRCR) ....................................................................... 170
Flow of the User Break Operation .................................................................... 173
Break on Instruction Fetch Cycle...................................................................... 174
Break on Data Access Cycle............................................................................. 175
Value of Saved Program Counter ..................................................................... 176
Usage Examples................................................................................................ 177
Cache Structure................................................................................................. 181
Cache Control Register 1 (CCR1) .................................................................... 184
Cache Control Register 2 (CCR2) .................................................................... 186
Searching Cache................................................................................................ 189
Read Access ...................................................................................................... 191
Prefetch Operation (Only for Operand Cache) ................................................. 191
Write Operation (Only for Operand Cache)...................................................... 191
Write-Back Buffer (Only for Operand Cache).................................................. 192
Coherency of Cache and External Memory ...................................................... 194
Address Array ................................................................................................... 194
Data Array......................................................................................................... 195
Usage Examples................................................................................................ 197
Notes ................................................................................................................. 198
Address Map ..................................................................................................... 203
Data Bus Width and Pin Function Setting for Individual Areas ....................... 204
CSn Control Register (CSnCNT) (n = 0 to 6)................................................... 207
CSn Recovery Cycle Setting Register (CSnREC) (n = 0 to 6) ......................... 209
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