DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 306

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
Table 9.19 Case for 32-Bit External Data Bus Width (BSIZE*
Notes: 1. The legend BSIZE represents the BSIZE bit in the SDRAMCm control register.
Page 278 of 1190
SDRAM
Type
Number
DSZ*
DDBW*
This LSI
address
A16 (/BA1)*
A15 (/BA0)*
A14 (/MA12)*
A13 (/MA11)*
A12 (/MA10)*
A11 (/MA9)*
A10 (/MA8)*
A9 (/MA7)*
A8 (/MA6)*
A7 (/MA5)*
A6 (/MA4)*
A5 (/MA3)*
A4 (/MA2)*
A3 (/MA1)*
A2 (/MA0)*
2
3
2. The legend DSZ represents the DSZ bit in the SDRAMm address register.
3. The legend DDBW represents the DDBW bit in the SDRAMm address register.
4. The legends BA1, BA0, and MA12 to MA0 represent the SDRAM bank address and
5. Addresses addr24 to addr0 are the logical addresses used by the CPU and DMAC in
6. When the RD, WR or PRA command is issued, this carries the pre-charge option
4
4
4
4
4
4
4
4
4
4
SDRAM address respectively.
access to the SDRAM.
signal.
4
4
4
4
4
Row
Address
addr22*
addr21*
L
L
addr20*
addr19*
addr18*
addr17*
addr16*
addr15*
addr14*
addr13*
addr12*
addr11*
addr10*
001 (8 Mbytes)
64 Mbits (×32)
10 (32 bits)
5
5
5
5
5
5
5
5
5
5
5
5
5
1
Column
Address
addr22*
addr21*
L
L
*
L
L
addr9*
addr8*
addr7*
addr6*
addr5*
addr4*
addr3*
addr2*
6
5
5
5
5
5
5
5
5
5
5
Row
Address
addr23*
addr22*
L
addr21*
addr20*
addr19*
addr18*
addr17*
addr16*
addr15*
addr14*
addr13*
addr12*
addr11*
addr10*
010 (16 Mbytes)
64 Mbits (×16)
01 (16 bits)
5
5
5
5
5
5
5
5
5
5
5
5
5
5
2
Column
Address
addr23*
addr22*
L
L
*
L
L
addr9*
addr8*
addr7*
addr6*
addr5*
addr4*
addr3*
addr2*
6
5
5
5
5
5
5
5
5
5
5
Row
Address
addr23*
addr22*
L
addr21*
addr20*
addr19*
addr18*
addr17*
addr16*
addr15*
addr14*
addr13*
addr12*
addr11*
addr10*
010 (16 Mbytes)
128 Mbits (×32)
10 (32 bits)
5
5
5
5
5
5
5
5
5
5
5
5
5
5
1
1
Column
Address
addr23*
addr22*
L
L
*
L
L
addr9*
addr8*
addr7*
addr6*
addr5*
addr4*
addr3*
addr2*
6
= (0, 1)) (1)
5
5
5
5
5
5
5
5
5
5
R01UH0026EJ0300 Rev. 3.00
Row
Address
addr24*
addr23*
L
addr22*
addr21*
addr20*
addr19*
addr18*
addr17*
addr16*
addr15*
addr14*
addr13*
addr12*
addr11*
011 (32 Mbytes)
64 Mbits (×8)
00 (8 bits)
5
5
5
5
5
5
5
5
5
5
5
5
5
5
SH7201 Group
4
Column
Address
addr24*
addr23*
L
L
*
L
addr10*
addr9*
addr8*
addr7*
addr6*
addr5*
addr4*
addr3*
addr2*
Sep 24, 2010
6
5
5
5
5
5
5
5
5
5
5
5