DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 902

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 19 Controller Area Network (RCAN-ET)
19.9
19.9.1
The standby control register 2 (STBCR2) controls the supply of clocks to RCAN-ET. As an initial
value, the clock to RCAN-ET is halted. Registers should be accessed after the module stop mode
is released.
19.9.2
Two types of resets are supported for RCAN-ET.
• Hardware reset
• Software reset
As the IRR0 bit in the interrupt request register (IRR) is initialized and set to 1 at a reset, it should
be cleared to 0 in the configuration mode shown in the reset sequence diagram.
The area except for the message control field 1 (CONTROL1) of Mailbox is consisted of RAM,
and not initialized at a reset. After a power-on reset, all the Mailboxes should be initialized in the
configuration mode shown in the reset sequence diagram.
19.9.3
The supply of main clocks in the modules is stopped in CAN sleep mode. Therefore, registers
other than MCR, GSR, IRR, and IMR should not be accessed in CAN sleep mode.
19.9.4
When the CAN bus receive frame is being stored in the Mailbox with the CAN communication
functions of RCAN-ET, accessing the Mailbox area generates 0 to 5 peripheral bus cycles as a
wait.
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RCAN-ET is initialized by a power-on reset, deep standby mode, or software standby mode.
The MCR0 bit in the master control register (MCR) initializes registers other than MCR and
CAN communication functions.
Usage Notes
Module Standby Mode
Reset
CAN Sleep Mode
Register Access
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010