DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 860

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 19 Controller Area Network (RCAN-ET)
Bit 4 — Halt/Sleep Status Bit (GSR4): Indicates whether the CAN engine is in the halt/sleep
state or not. Please note that the clearing time of this flag is not the same as the setting time of
IRR12.
Please note that this flag reflects the status of the CAN engine and not of the full RCAN-ET IP.
RCAN-ET exits sleep mode and can be accessed once MCR5 is cleared. The CAN engine exits
sleep mode only after two additional transmission clocks on the CAN Bus.
Bit 3 — Reset Status Bit (GSR3): Indicates whether the RCAN-ET is in the reset state or not.
Bit 2 — Message Transmission in progress Flag (GSR2): Flag that indicates to the CPU if the
RCAN-ET is in Bus Off or transmitting a message or an error/overload flag due to error detected
during transmission. The timing to set TXACK is different from the time to clear GSR2. TXACK
is set at the 7
messages ready to be transmitted. It is also set by arbitration lost, bus idle, reception, reset or halt
transition.
Page 832 of 1190
Bit 4: GSR4
0
1
Bit 3: GSR3
0
1
Bit 2: GSR2
0
1
th
bit of End Of Frame. GSR2 is set at the 3
Description
RCAN-ET is not in the Halt state or Sleep state (Initial value)
Halt mode (if MCR1 = 1) or Sleep mode (if MCR5 = 1)
[Setting condition] If MCR1 is set and the CAN bus is either in intermission or
idle or MCR5 is set and RCAN-ET is in the halt mode or RCAN-ET is moving
to Bus Off when MCR14 and MCR6 are both set
Description
RCAN-ET is not in the reset state
Reset state (Initial value)
[Setting condition] After an RCAN-ET internal reset (due to SW or HW reset)
Description
RCAN-ET is in Bus Off or a transmission is in progress
[Setting condition] Not in Bus Off and no transmission in progress (Initial
value)
rd
bit of intermission if there are no more
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010