DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 37

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
1.3
The block diagram of this LSI is shown in figure 1.1.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
External
bus I/O
External bus
width
mode input
Block Diagram
SH-2A CPU
Pin function
Bus state
controller
controller
User debugging
(PFC)
(BSC)
core
JTAG I/O
memory (8 kbytes)
Instruction cache
interface
(H-UDI)
Port
General I/O
Cache controller
module bus 1
peripheral
controller
Bus bridge
On-chip
I/O port
Port
mode control
Power-down
Floating-point
memory (8 kbytes)
unit (FPU)
Operand cache
module bus 2
EXTAL input
XTAL output
CKIO I/O
Clock mode input
Figure 1.1 Block Diagram
peripheral
controller
On-chip
Clock pulse
Analog output
generator
(CPG)
Port
converter
(DAC)
D/A
Port
(32 kbytes)
WDTOVF output
On-chip
RAM
monitor
Bus
Analog input
ADTRG input
Watchdog
converter
(WDT)
timer
(ADC)
Port
A/D
Port
access controller
User break
Direct memory
controller
(UBC)
(DMAC)
area network
RES input
MRES input
NMI input
IRQ input
PINT input
CAN bus I/O
(RCAN-ET)
Controller
controller
Interrupt
(INTC)
Port
Port
On-chip peripheral
module bus 1
Serial I/O
Audio clock input
Serial sound
Timer pulse I/O
interface
Multi-function
timer pulse
UBCTRG
output
(SSI)
Port
(MTU2)
unit 2
CPU instruction fetch bus (F bus)
CPU memory access bus (M bus)
DREQ input
DACK output
DACT output
DTEND output
Port
Compare match output
External counter clock input
External counter reset input
Advanced user
I
interface 3
2
debugger-II
I
C bus I/O
2
(IIC3)
(AUD-II)
C bus
Port
On-chip peripheral module bus 2
8-bit timer
Internal bus (I bus)
(TMR)
Port
Internal CPU bus
Internal DMA write bus
Internal DMA read bus
communication
interface with
FIFO (SCIF)
Section 1 Overview
Serial I/O
Serial
Port
RTC_X2 output
RTC_X1 input
Page 9 of 1190
Realtime
AUDRST input
AUDSYNC input
AUDCK input
AUDMD input
AUDATA I/O
(RTC)
clock
Port
CPU bus
(C bus)