DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 369

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Cycle steal transfer mode (transfer between different BIU)
Cycle steal transfer mode (transfer in the same BIU)
Pipeline transfer mode (transfer between different BIU)
Figure 11.2 Examples of the Alternation of Bus Mastership between the DMAC
System clock
System clock
System clock
DMAC
CPU
DMAC
CPU
DMAC
CPU
(1) CPU access to other than BIU on DMAC read side is possible
(2) CPU access to other than BIU on DMAC write side is possible
(3) CPU access to other than BIU on DMAC read/write side is possible
(4) CPU access to other than BIU on DMAC read side is possible
(5) CPU access to other than BIU on DMAC read/write side is possible
(6) CPU access to other than BIU on DMAC write side is possible
However, when a DMA access to external address space followed by CPU access to external address
space is occurred, CPU access next to DMA cycle may not be occurred.
Read
Read
Read
(1)
(3)
(4)
Single operand transfer
Single operand transfer
Single operand transfer
and CPU in Various DMA Transfer Modes
Read
Write
Write
Read
Write
(2)
(3)
(5)
Read
Read
Read
Write
(1)
Write
(6)
Write
Write
Write
(2)
(3)
Read
Read
Read
(1)
(3)
(4)
Single operand transfer
Single operand transfer
Single operand transfer
Section 11 Direct Memory Access Controller (DMAC)
Read
Write
Write
Read
Write
(2)
(3)
(5)
Read
Read
Read
Write
(1)
Write
(6)
Write
Write
Write
(2)
(3)
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