DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 577
![IC SH7201 MPU ROMLESS 176LQFP](/photos/28/61/286154/176-lqfp_sml.jpg)
DS72011RB120FPV
Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet
1.R0K572011S000BE.pdf
(1222 pages)
Specifications of DS72011RB120FPV
Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 577 of 1222
- Download datasheet (8Mb)
SH7201 Group
12.7.3
When counter clearing on compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
• Channels 0 to 4
• Channel 5
Where
12.7.4
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes
precedence and the TCNT write is not performed.
Figure 12.109 shows the timing in this case.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
f =
f =
Caution on Period Setting
Contention between TCNT Write and Clear Operations
f:
Pφ:
N:
Figure 12.109 Contention between TCNT Write and Clear Operations
(N + 1)
P
Address
Write signal
Counter clear
signal
TCNT
Pφ
Pφ
N
Counter frequency
MTU2 peripheral clock operating frequency
TGR set value
TCNT write cycle
N
TCNT address
T1
T2
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
H'0000
Page 549 of 1190
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