DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 757

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

SH7201 Group
The I
interface functions. However, the configuration of the registers that control the I
partly from the Philips register configuration.
17.1
• Selection of I
• Continuous transmission/reception
I
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization/wait function
• Six interrupt sources
• The direct memory access controller (DMAC) can be activated by a transmit-data-empty
• Direct bus drive
Clocked synchronous serial format:
• Four interrupt sources
• The direct memory access controller (DMAC) can be activated by a transmit-data-empty
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
2
C bus format:
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically. If transmission/reception is not yet possible, set the SCL to low until
preparations are completed.
Transmit data empty (including slave-address match), transmit end, receive data full (including
slave-address match), arbitration lost, NACK detection, and stop condition detection
request or receive-data-full request to transfer data.
Two pins, SCL0 to SCL2 and SDA0 to SDA2, function as NMOS open-drain outputs when the
bus drive function is selected.
Transmit-data-empty, transmit-end, receive-data-full, and overrun error
request or receive-data-full request to transfer data.
2
C bus interface 3 conforms to and provides a subset of the Philips I
Features
2
C format or clocked synchronous serial format
Section 17 I
2
C Bus Interface 3 (IIC3)
Section 17 I
2
C (Inter-IC) bus
2
2
C Bus Interface 3 (IIC3)
C bus differs
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