DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 256

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
9.4.13
SDmADR specifies the data bus width and the channel size of SDRAM.
Page 228 of 1190
Bit
31 to 10 ⎯
9, 8
7 to 3
2 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
SDRAMm Address Register (SDmADR) (m = 0, 1)
Bit Name
DDBW[1:0] Undefined R/W
⎯
DSZ[2:0]
31
—
15
—
R
R
0
0
30
—
14
—
R
R
0
0
29
—
13
—
Initial
Value
All 0
All 0
Undefined R/W
R
R
0
0
28
—
12
—
R
R
0
0
27
11
—
—
R
R
0
0
R/W
R
R
26
10
—
—
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
SDRAM Data Bit Width Setting
These bits specify the width of the SDRAM bus.
00: 8 bits
01: 16 bits
10: 32 bits
11: Setting prohibited
Reserved
These bits are always read as 0. The write value
should always be 0.
Channel Size Setting
These bits specify the size of channels 0 and 1. If a
size smaller than SDRAM area 0 or 1 is selected, ghost
memory will result. When accessing 32-bit data in
SDRAM with a 16-bit bus width, the 16 bits of the first
half of the address (A1 = 0) are accessed first, and
then the 16 bits of the second half of the address (A1 =
1) are accessed.
DDBW[1:0]
R/W
25
—
—
R
0
9
R/W
24
—
—
R
0
8
23
—
—
R
R
0
7
0
22
—
—
R
R
0
6
0
21
—
—
R
R
0
5
0
20
—
—
R
R
0
4
0
R01UH0026EJ0300 Rev. 3.00
19
—
—
R
R
0
3
0
R/W
18
—
—
R
0
2
DSZ[2:0]
SH7201 Group
R/W
17
—
Sep 24, 2010
—
R
0
1
R/W
16
—
—
R
0
0