DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 82

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 2 CPU
2.4.7
Table 2.16 System Control Instructions
Page 54 of 1190
Instruction
CLRT
CLRMAC
LDBANK
LDC
LDC
LDC
LDC
LDC.L
LDC.L
LDC.L
LDS
LDS
LDS
LDS.L
LDS.L
LDS.L
NOP
RESBANK
RTE
SETT
SLEEP
STBANK
@Rm,R0
Rm,SR
Rm,TBR
Rm,GBR
Rm,VBR
@Rm+,SR
@Rm+,GBR
@Rm+,VBR
Rm,MACH
Rm,MACL
Rm,PR
@Rm+,MACH
@Rm+,MACL
@Rm+,PR
R0,@Rn
System Control Instructions
Instruction Code
0000000000001000
0000000000101000
0100mmmm11100101
0100mmmm00001110
0100mmmm01001010
0100mmmm00011110
0100mmmm00101110
0100mmmm00000111
0100mmmm00010111
0100mmmm00100111
0100mmmm00001010
0100mmmm00011010
0100mmmm00101010
0100mmmm00000110
0100mmmm00010110
0100mmmm00100110
0000000000001001
0000000001011011
0000000000101011
0000000000011000
0000000000011011
0100nnnn11100001
Operation
0 → T
0 → MACH,MACL
(Specified register bank entry)
→ R0
Rm → SR
Rm → TBR
Rm → GBR
Rm → VBR
(Rm) → SR, Rm + 4 → Rm
(Rm) → GBR, Rm + 4 → Rm
(Rm) → VBR, Rm + 4 → Rm
Rm → MACH
Rm → MACL
Rm → PR
(Rm) → MACH, Rm + 4 → Rm 1
(Rm) → MACL, Rm + 4 → Rm 1
(Rm) → PR, Rm + 4 → Rm
No operation
Bank → R0 to R14, GBR,
MACH, MACL, PR
Delayed branch,
stack area → PC/SR
1 → T
Sleep
R0 →
(specified register bank entry)
Execu-
tion
Cycles
1
1
6
3
1
1
1
5
1
1
1
1
1
1
1
9*
6
1
5
7
R01UH0026EJ0300 Rev. 3.00
T Bit
0
⎯
⎯
LSB
⎯
⎯
⎯
LSB
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
1
⎯
⎯
SH2,
SH2E SH4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Compatibility
SH7201 Group
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Sep 24, 2010
SH-2A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes