DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 382

IC SH7201 MPU ROMLESS 176LQFP

DS72011RB120FPV

Manufacturer Part Number
DS72011RB120FPV
Description
IC SH7201 MPU ROMLESS 176LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheet

Specifications of DS72011RB120FPV

Core Size
32-Bit
Core Processor
SH-2A
Speed
120MHz
Connectivity
CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
104
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 70°C
Package / Case
176-LQFP
No. Of I/o's
109
Ram Memory Size
32KB
Cpu Speed
120MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V
Operating Temperature Range
-20°C To +70°C
Embedded Interface Type
I2C, SSI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Program Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS72011RB120FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 11 Direct Memory Access Controller (DMAC)
11.7.3
When pins DREQ0 to DREQ3 (DCTG = "000001" to "000100") are specified by the DMA
request source selection bits (DTCG), either level sense or edge sense might be required. Make the
appropriate setting ("01" or "11" for level sense and "00" or "10" for edge sense) in the input sense
selection bits (STRG) of DMA control register A (DMCNTAn).
When the software trigger (DCTG = "000000") is selected as a DMA request source, set these bits
to "00" to select the rising-edge sense. When IIC3, SCIF, SSI, RCAN-ET, MTU2, or ADC
(DCTG = "000101" to "100101") is selected, set the bits to "10" to select the falling-edge sense.
Table 11.4 shows the relationships between the DMA request sources and input sense mode.
Below are further details on level- and edge-sense operation.
(1)
When a level sense is specified (STRG = "01" or "11"), one level of the DMA request signal
indicates the DMA request. Since DMA requests detected in this way are not retained in the
DMAC, maintain the requesting level until acceptance of the DMA request has been confirmed.
Figure 11.7 is an example of DMA request reception processing when a level sense has been
selected.
When a level sense has been selected, DMA request bit for the channel is masked over the period
from the start of the last write access of single operand transfer until four clock pulses (system
Page 354 of 1190
Level Sense
System clock
DMA state
DMA request input
DMA acknowledge
output
DMA request bit
[Legend]
Figure 11.7 Example of DMA Request Reception Processing for a Level Sense
(low level sense)
Sense Mode for DMA Requests
: Sampling point for DMA request
Maintain DMA request level until DMA acknowledge output
is activated to indicate acceptance of the request
Start of single operand transfer
Read
R01UH0026EJ0300 Rev. 3.00
Write
SH7201 Group
Sep 24, 2010

Related parts for DS72011RB120FPV