DS72011RB120FPV Renesas Electronics America, DS72011RB120FPV Datasheet - Page 56

• Manufacturer Part Number: DS72011RB120FPV
• Description: IC SH7201 MPU ROMLESS 176LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of DS72011RB120FPV

• Core Size: 32-Bit
• Core Processor: SH-2A
• Speed: 120MHz
• Connectivity: CAN, EBI/EMI, FIFO, I²C, SCI, Serial Sound
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 176-LQFP
• No. Of I/o's: 109
• Ram Memory Size: 32KB
• Cpu Speed: 120MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V
• Operating Temperature Range: -20°C To +70°C
• Embedded Interface Type: I2C, SSI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K572011S000BE - KIT STARTER FOR SH7201HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 2 CPU
(9)
The T bit in the status register (SR) changes according to the result of the comparison. Whether a
conditional branch is taken or not taken depends upon the T bit condition (true/false). The number
of instructions that change the T bit is kept to a minimum to improve the processing speed.
Table 2.4
(10) Immediate Data
Byte immediate data is located in an instruction code. Word or longword immediate data is not
located in instruction codes but in a memory table. The memory table is accessed by an immediate
data transfer instruction (MOV) using the PC relative addressing mode with displacement.
With the SH-2A, 17- to 28-bit immediate data can be located in an instruction code. However, for
21- to 28-bit immediate data, an OR instruction must be executed after the data is transferred to a
register.
Table 2.5
Note: @(disp, PC) accesses the immediate data.
Page 28 of 1190
SH-2A CPU
CMP/GE
BT
BF
ADD
CMP/EQ
BT
Classification
8-bit immediate
16-bit immediate
20-bit immediate
28-bit immediate
32-bit immediate
T Bit
R1,R0
TRGET0
TRGET1
#−1,R0
#0,R0
TRGET
T Bit
Immediate Data Accessing
SH-2A CPU
MOV
MOVI20
MOVI20
MOVI20S
OR
MOV.L
.DATA.L
Description
T bit is set when R0 ≥ R1.
The program branches to TRGET0
when R0 ≥ R1 and to TRGET1
when R0 < R1.
T bit is not changed by ADD.
T bit is set when R0 = 0.
The program branches if R0 = 0.
#H'12,R0
#H'1234,R0
#H'12345,R0
#H'12345,R0
#H'67,R0
@(disp,PC),R0
.................
H'12345678
Example of Other CPU
MOV.B
MOV.W
MOV.L
MOV.L
MOV.L
Example of Other CPU
CMP.W
BGE
BLT
SUB.W
BEQ
#H'12,R0
#H'1234,R0
#H'12345,R0
#H'1234567,R0
#H'12345678,R0
R1,R0
TRGET0
TRGET1
#1,R0
TRGET
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010